Ultra thin ultrafine-pitch chip-package interconnections for embedded chip last approach
Ever growing demands for portability and functionality have always governed the electronic technology innovations. IC downscaling with Moore s law and system miniaturization with System-On-Package (SOP) paradigm has resulted and will continue to result in ultraminiaturized systems with unprecedented...
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ndltd-GATECH-oai-smartech.gatech.edu-1853-225942013-01-07T20:25:48ZUltra thin ultrafine-pitch chip-package interconnections for embedded chip last approachMehrotra, GauravACFAdhesiveCopper bumpFine pitchInterconnectionsNCFReliabilityMetal bondingCopperInterconnects (Integrated circuit technology)Microelectronic packagingEver growing demands for portability and functionality have always governed the electronic technology innovations. IC downscaling with Moore s law and system miniaturization with System-On-Package (SOP) paradigm has resulted and will continue to result in ultraminiaturized systems with unprecedented functionality at reduced cost. The trend towards 3D silicon system integration is expected to downscale IC I/O pad pitches from 40µm to 1- 5 µm in future. Device- to- system board interconnections are typically accomplished today with either wire bonding or solders. Both of these are incremental and run into either electrical or mechanical barriers as they are extended to higher density of interconnections. Alternate interconnection approaches such as compliant interconnects typically require lengthy connections and are therefore limited in terms of electrical properties, although expected to meet the mechanical requirements. As supply currents will increase upto 220 A by 2012, the current density will exceed the maximum allowable current density of solders. The intrinsic delay and electromigration in solders are other daunting issues that become critical at nanometer size technology nodes. In addition, formation of intermetallics is also a bottleneck that poses significant mechanical issues. Recently, many research groups have investigated various techniques for copper-copper direct bonding. Typically, bonding is carried out at 400oC for 30 min followed by annealing for 30 min. High thermal budget in such process makes it less attractive for integrated systems because of the associated process incompatibilities. In the present study, copper-copper bonding at ultra fine-pitch using advanced nano-conductive and non-conductive adhesives is evaluated. The proposed copper-copper based interconnects using advanced conductive and non-conductive adhesives will be a new fundamental and comprehensive paradigm to solve all the four barriers: 1) I/O pitch 2) Electrical performance 3) Reliability and 4) Cost. This thesis investigates the mechanical integrity and reliability of copper-copper bonding using advanced adhesives through test vehicle fabrication and reliability testing. Test vehicles were fabricated using low cost electro-deposition techniques and assembled onto glass carrier. Experimental results show that proposed copper-copper bonding using advanced adhesives could potentially meet all the system performance requirements for the emerging micro/nano-systems.Georgia Institute of Technology2008-06-10T20:39:24Z2008-06-10T20:39:24Z2008-03-18Thesishttp://hdl.handle.net/1853/22594 |
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ACF Adhesive Copper bump Fine pitch Interconnections NCF Reliability Metal bonding Copper Interconnects (Integrated circuit technology) Microelectronic packaging |
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ACF Adhesive Copper bump Fine pitch Interconnections NCF Reliability Metal bonding Copper Interconnects (Integrated circuit technology) Microelectronic packaging Mehrotra, Gaurav Ultra thin ultrafine-pitch chip-package interconnections for embedded chip last approach |
description |
Ever growing demands for portability and functionality have always governed the electronic technology innovations. IC downscaling with Moore s law and system miniaturization with System-On-Package (SOP) paradigm has resulted and will continue to result in ultraminiaturized systems with unprecedented functionality at reduced cost. The trend towards 3D silicon system integration is expected to downscale IC I/O pad pitches from 40µm to 1- 5 µm in future. Device- to- system board interconnections are typically accomplished today with either wire bonding or solders. Both of these are incremental and run into either electrical or mechanical barriers as they are extended to higher density of interconnections. Alternate interconnection approaches such as compliant interconnects typically require lengthy connections and are therefore limited in terms of electrical properties, although expected to meet the mechanical requirements. As supply currents will increase upto 220 A by 2012, the current density will exceed the maximum allowable current density of solders. The intrinsic delay and electromigration in solders are other daunting issues that become critical at nanometer size technology nodes. In addition, formation of intermetallics is also a bottleneck that poses significant mechanical issues.
Recently, many research groups have investigated various techniques for copper-copper direct bonding. Typically, bonding is carried out at 400oC for 30 min followed by annealing for 30 min. High thermal budget in such process makes it less attractive for integrated systems because of the associated process incompatibilities. In the present study, copper-copper bonding at ultra fine-pitch using advanced nano-conductive and non-conductive adhesives is evaluated. The proposed copper-copper based interconnects using advanced conductive and non-conductive adhesives will be a new fundamental and comprehensive paradigm to solve all the four barriers: 1) I/O pitch 2) Electrical performance 3) Reliability and 4) Cost. This thesis investigates the mechanical integrity and reliability of copper-copper bonding using advanced adhesives through test vehicle fabrication and reliability testing. Test vehicles were fabricated using low cost electro-deposition techniques and assembled onto glass carrier. Experimental results show that proposed copper-copper bonding using advanced adhesives could potentially meet all the system performance requirements for the emerging micro/nano-systems. |
author |
Mehrotra, Gaurav |
author_facet |
Mehrotra, Gaurav |
author_sort |
Mehrotra, Gaurav |
title |
Ultra thin ultrafine-pitch chip-package interconnections for embedded chip last approach |
title_short |
Ultra thin ultrafine-pitch chip-package interconnections for embedded chip last approach |
title_full |
Ultra thin ultrafine-pitch chip-package interconnections for embedded chip last approach |
title_fullStr |
Ultra thin ultrafine-pitch chip-package interconnections for embedded chip last approach |
title_full_unstemmed |
Ultra thin ultrafine-pitch chip-package interconnections for embedded chip last approach |
title_sort |
ultra thin ultrafine-pitch chip-package interconnections for embedded chip last approach |
publisher |
Georgia Institute of Technology |
publishDate |
2008 |
url |
http://hdl.handle.net/1853/22594 |
work_keys_str_mv |
AT mehrotragaurav ultrathinultrafinepitchchippackageinterconnectionsforembeddedchiplastapproach |
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1716474824911486976 |