A Novel Analog Decision-Feedback Equalizer in CMOS for Serial 10-Gb/sec Data Transmission Systems
This dissertation develops an unclocked receiver analog decision-feedback equalizer (ADFE) circuit architecture and topology and implements the circuit in 0.18-um CMOS to enable 10-Gb/sec serial baseband data transmission over FR-4 backplane and optical fibre. The ADFE overcomes the first feedback-l...
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Georgia Institute of Technology
2008
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Online Access: | http://hdl.handle.net/1853/19847 |