Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs

Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs

<p>As integrated circuits (ICs) continue to scale to smaller dimensions, long interconnects</p><p>have become the dominant contributor to circuit delay and a significant component of</p><p>power consumption. In order to reduce the length of these interconnects, 3D integ...

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Bibliographic Details
Main Author: Noia, Brandon Robert
Other Authors: Chakrabarty, Krishnendu
Published: 2014
Subjects:
Electrical engineering
Computer engineering
3D SIC
DFT
TSV
Online Access:http://hdl.handle.net/10161/8666

Internet

http://hdl.handle.net/10161/8666

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