Verspannungstechniken zur Leistungssteigerung von SOI-CMOS-Transistoren

Verspannungstechniken zur Leistungssteigerung von SOI-CMOS-Transistoren

Mit dem Erreichen der Grenzen der konventionellen MOSFET-Skalierung werden neue Techniken untersucht, um die Leistungsfähigkeit der CMOS-Technologie dem bisherigen Trend folgend weiter zu steigern. Einer dieser Ansätze ist die Verwendung mechanischer Verspannungen im Transistorkanal. Mechanische Ver...

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Bibliographic Details
Main Author:	Flachowsky, Stefan
Other Authors:	Technische Universität Dresden, Fakultät Elektrotechnik und Informationstechnik
Format:	Doctoral Thesis
Language:	deu
Published:	Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden 2010
Subjects:	CMOS Verspannungstechniken verspanntes Silizium Skalierung mechanisch verspannte Transistoren TCAD Ladungsträgerbeweglichkeit stress techniques strained silicon scaling mechanicaly stressed transistors carrier mobility ddc:620 rvk:ZN 4960
Online Access:	http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-63136 http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-63136 http://www.qucosa.de/fileadmin/data/qucosa/documents/6313/Stefan%20Flachowsky%20-%20Dissertation%202010.pdf

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