Models, Design Methods and Tools for Improved Partial Dynamic Reconfiguration

Models, Design Methods and Tools for Improved Partial Dynamic Reconfiguration

Partial dynamic reconfiguration of FPGAs has attracted high attention from both academia and industry in recent years. With this technique, the functionality of the programmable devices can be adapted at runtime to changing requirements. The approach allows designers to use FPGAs more efficiently: E....

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Bibliographic Details
Main Author: Rullmann, Markus
Other Authors: Technische Universität Dresden, Fakultät Elektrotechnik und Informationstechnik
Format: Doctoral Thesis
Language:English
Published: Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden 2010
Subjects:
FPGA
High-Level-Synthese
Rekonfigurationskosten
Dynamische Rekonfiguration
Partielle Rekonfiguration
Kostenoptimierung
High-Level-Synthesis
Reconfiguration Cost
Dynamic Reconfiguration
Partial Reconfiguration
Cost Optimization
ddc:620
rvk:ZN 4940
Field programmable gate array
Technische Informatik
Rekonfiguration
Netzwerksynthese
EDA <Optimierung>
Entwurfsautomation
Schaltungsentwurf
System-on-Chip
Online Access:http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-61526
http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-61526
http://www.qucosa.de/fileadmin/data/qucosa/documents/6152/dissertation_1.pdf

Internet

http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-61526
http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-61526
http://www.qucosa.de/fileadmin/data/qucosa/documents/6152/dissertation_1.pdf

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