Electrical Characterisation of Ferroelectric Field Effect Transistors based on Ferroelectric HfO2 Thin Films

• Main Author: Yurchuk, Ekaterina
• Other Authors: Technische Universität Dresden, Fakultät Elektrotechnik und Informationstechnik
• Format: Doctoral Thesis
• Language: English
• Published: Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden 2015
• Subjects: Nichtflüchtiger Halbleiterpeicher; Ferroelektrische Speicher; Ferroelektrischer transistor; Hafniumoxid; Ferroelektrische Dünnschichten; Nonvolatile semiconductor memory; ferroelectric memory transistor; FeFET; ferroelectric field effect transistor; ferroelectric thin films; hafnium oxide; ddc:621.3; rvk:ZN 4870; rvk:ZN 3430; Speicher; Halbleiterspeicher; MOS-Speicher; Nichtflüchtiger Speicher; Elektrischer Speicher; Speicherelement; Feldeffekttransistor; Ferroelektrischer Transistor; Hafniumdioxid; Dünne Schicht
• Online Access: http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-172000; http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-172000; http://www.qucosa.de/fileadmin/data/qucosa/documents/17200/Dissertation_Yurchuk_final_PDF_ISO.pdf

Ferroelectric field effect transistor (FeFET) memories based on a new type of ferroelectric material (silicon doped hafnium oxide) were studied within the scope of the present work. Utilisation of silicon doped hafnium oxide (Si:HfO2) thin films instead of conventional perovskite ferroelectrics as a functional layer in FeFETs provides compatibility to the CMOS process as well as improved device scalability. The influence of different process parameters on the properties of Si:HfO2 thin films was analysed in order to gain better insight into the occurrence of ferroelectricity in this system. A subsequent examination of the potential of this material as well as its possible limitations with the respect to the application in non-volatile memories followed. The Si:HfO2-based ferroelectric transistors that were fully integrated into the state-of-the-art high-k metal gate CMOS technology were studied in this work for the first time. The memory performance of these devices scaled down to 28 nm gate length was investigated. Special attention was paid to the charge trapping phenomenon shown to significantly affect the device behaviour.