FIFO Buffering Transceiver: A Communication Chip Set for Multiprocessor Systems
<p>This thesis describes a family of VLSI chips designed to link a number of processors on a one-to-one basis. With these chips as communication system building blocks, a complex multiprocessor system can be built. Inter-processor communication within the multiprocessor system is accomplished...
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| Format: | Others |
| Language: | en |
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1982
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| Online Access: | https://thesis.library.caltech.edu/6928/1/Ng_ch_1982.pdf Ng, Charles H. (1982) FIFO Buffering Transceiver: A Communication Chip Set for Multiprocessor Systems. Master's thesis, California Institute of Technology. doi:10.7907/vdzd-7h35. https://resolver.caltech.edu/CaltechTHESIS:04132012-082850723 <https://resolver.caltech.edu/CaltechTHESIS:04132012-082850723> |
Internet
https://thesis.library.caltech.edu/6928/1/Ng_ch_1982.pdfNg, Charles H. (1982) FIFO Buffering Transceiver: A Communication Chip Set for Multiprocessor Systems. Master's thesis, California Institute of Technology. doi:10.7907/vdzd-7h35. https://resolver.caltech.edu/CaltechTHESIS:04132012-082850723 <https://resolver.caltech.edu/CaltechTHESIS:04132012-082850723>