Floating-Point Sparse Matrix-Vector Multiply for FPGAs

Floating-Point Sparse Matrix-Vector Multiply for FPGAs

<p>Large, high density FPGAs with high local distributed memory bandwidth surpass the peak floating-point performance of high-end, general-purpose processors. Microprocessors do not deliver near their peak floating-point performance on efficient algorithms that use the Sparse Matrix-Vector Mul...

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Bibliographic Details
Main Author: deLorimier, Michael John
Format: Others
Published: 2005
Online Access:https://thesis.library.caltech.edu/1776/1/smvm_thesis.pdf
deLorimier, Michael John (2005) Floating-Point Sparse Matrix-Vector Multiply for FPGAs. Master's thesis, California Institute of Technology. doi:10.7907/FCCD-FA51. https://resolver.caltech.edu/CaltechETD:etd-05132005-144347 <https://resolver.caltech.edu/CaltechETD:etd-05132005-144347>

Internet

https://thesis.library.caltech.edu/1776/1/smvm_thesis.pdf
deLorimier, Michael John (2005) Floating-Point Sparse Matrix-Vector Multiply for FPGAs. Master's thesis, California Institute of Technology. doi:10.7907/FCCD-FA51. https://resolver.caltech.edu/CaltechETD:etd-05132005-144347 <https://resolver.caltech.edu/CaltechETD:etd-05132005-144347>

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