Low-Voltage Analog CMOS Architectures and Design Methods
This dissertation develops design methods and architectures which allow analog circuits to operate at VT + 2Vds,sat, the minimum supply for CMOS circuits with all transistors in the active region where Vds,sat is the drain to source saturation voltage of a MOS transistor. Techniques which meet this...
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| Format: | Others |
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BYU ScholarsArchive
2007
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| Online Access: | https://scholarsarchive.byu.edu/etd/1218 https://scholarsarchive.byu.edu/cgi/viewcontent.cgi?article=2217&context=etd |