Technique for Efficient Evaluation of SRAM Timing Failure

• Main Authors: Qazi, Masood (Contributor), Tikekar, Mehul (Contributor), Dolecek, Lara (Author), Shah, Devavrat (Contributor), Chandrakasan, Anantha P. (Contributor)
• Other Authors: Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science (Contributor)
• Format: Article
• Language: English
• Published: Institute of Electrical and Electronics Engineers (IEEE), 2015-02-06T16:31:23Z.
• Subjects: Article
• Online Access: Get fulltext

 This brief presents a technique to evaluate the timing variation of static random access memory (SRAM). Specifically, a method called loop flattening, which reduces the evaluation of the timing statistics in the complex highly structured circuit to that of a single chain of component circuits, is justified. Then, to very quickly evaluate the timing delay of a single chain, a statistical method based on importance sampling augmented with targeted high-dimensional spherical sampling can be employed. The overall methodology has shown 650× or greater speedup over the nominal Monte Carlo approach with 10.5% accuracy in probability. Examples based on both the large-signal and small-signal SRAM read path are discussed, and a detailed comparison with state-of-the-art accelerated statistical simulation techniques is given.