A hardware spinal decoder
Spinal codes are a recently proposed capacity-achieving rateless code. While hardware encoding of spinal codes is straightforward, the design of an efficient, high-speed hardware decoder poses significant challenges. We present the first such decoder. By relaxing data dependencies inherent in the cl...
| Main Authors: | , , , , |
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| Other Authors: | |
| Format: | Article |
| Language: | English |
| Published: |
Association for Computing Machinery (ACM),
2014-03-28T15:37:01Z.
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| Subjects: | |
| Online Access: | Get fulltext |