Garnet: A Detailed on-Chip Network Model inside a Full-System Simulator
Until very recently, microprocessor designs were computation-centric. On-chip communication was frequently ignored. This was because of fast, single-cycle on-chip communication. The interconnect power was also insignificant compared to the transistor power. With uniprocessor designs providing dimini...
| Main Authors: | , , , |
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| Other Authors: | |
| Format: | Article |
| Language: | English |
| Published: |
Institute of Electrical and Electronics Engineers (IEEE),
2012-10-01T15:55:56Z.
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| Subjects: | |
| Online Access: | Get fulltext |