A 6-bit, 0.2 V to 0.9 V Highly Digital Flash ADC With Comparator Redundancy

• Main Authors: Daly, Denis C. (Author), Chandrakasan, Anantha P. (Contributor)
• Other Authors: Massachusetts Institute of Technology. Microsystems Technology Laboratories (Contributor)
• Format: Article
• Language: English
• Published: Institute of Electrical and Electronics Engineers, 2010-03-11T14:32:46Z.
• Subjects: Article
• Online Access: Get fulltext

 A 6-bit highly digital flash ADC is implemented in a 0.18 mum CMOS process. The ADC operates in the subthreshold regime down to 200 mV and employs comparator redundancy and reconfigurability to improve linearity. The low-voltage sampling switch employs voltage boosting, stacking and feedback to reduce leakage. Common-mode rejection is implemented digitally via an IIR filter. The minimum FOM of the ADC is 125 fJ/conversion-step at a 0.4 V supply, where it achieves an ENOB of 5.05 at 400 kS/s. The clocked comparators' switching thresholds are adjusted through a combination of device sizing and stacking. A quadratic relationship between the amount of device stacking and the strength of an input network in the subthreshold regime is derived, demonstrating an advantage of stacking over device width scaling to adjust comparator thresholds.