A 6-bit, 0.2 V to 0.9 V Highly Digital Flash ADC With Comparator Redundancy
A 6-bit highly digital flash ADC is implemented in a 0.18 mum CMOS process. The ADC operates in the subthreshold regime down to 200 mV and employs comparator redundancy and reconfigurability to improve linearity. The low-voltage sampling switch employs voltage boosting, stacking and feedback to redu...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Article |
| Language: | English |
| Published: |
Institute of Electrical and Electronics Engineers,
2010-03-11T14:32:46Z.
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| Subjects: | |
| Online Access: | Get fulltext |