Sub-Thermal Subthreshold Characteristics in Top-Down InGaAs/InAs Heterojunction Vertical Nanowire Tunnel FETs

• Main Authors: Zhao, Xin (Author), Vardi, Alon (Author), del Alamo, Jesus A (Author)
• Other Authors: Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science (Contributor)
• Format: Article
• Language: English
• Published: Institute of Electrical and Electronics Engineers (IEEE), 2020-07-14T02:21:48Z.
• Subjects: Article
• Online Access: Get fulltext

 This letter demonstrates top-down InGaAs/InAs heterojunction vertical nanowire tunnel FETs with sub-thermal subthreshold characteristics over two orders of magnitude of current. A minimal subthreshold swing of 53 mV/decade at V[subscript ds] = 0.3 V has been obtained at room temperature. An I[subscript 60] (defined as the highest current level where the subthreshold characteristics exhibit a transition from sub- to super-60 mV/decade behavior) of 4.3 nA/μm has been achieved at V s = 0.3 V. Compared with an earlier device generation, much reduced temperature dependence of the subthreshold characteristics is observed in this letter. The major difference between the two device generations is the drastically reduced interface trap density, evidenced by the improvement in the subthreshold swing of InGaAs vertical nanowire MOSFETs fabricated at the same time. This result suggests oxide-semiconductor interface trap-assisted tunnelling the main leakage mechanism in III-V TFETs fabricated by our process. The improvement in the interface quality has been enabled by improved gate oxide deposition and post-deposition treatment.