Fabrication and Thermal Budget Considerations of Advanced Ge and InP SOLES Substrates

Fabrication and Thermal Budget Considerations of Advanced Ge and InP SOLES Substrates

The Silicon on Lattice Engineered Substrate (SOLES) platform enables monolithic integration of III-V compound semiconductor (III-V) and silicon (Si) complementary metal oxide semiconductor (CMOS) devices. The SOLES wafer provides a device quality Si-on-Insulator (SOI) layer for CMOS device fabricati...

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Bibliographic Details
Main Authors: Pacella, Nan Y. (Contributor), Bulsara, Mayank (Contributor), Drazek, Charlotte (Author), Guiot, Eric (Author), Fitzgerald, Eugene A (Author)
Other Authors: Massachusetts Institute of Technology. Materials Processing Center (Contributor), Massachusetts Institute of Technology. Department of Materials Science and Engineering (Contributor), Fitzgerald, Eugene A. (Contributor)
Format: Article
Language:English
Published: Electrochemical Society, 2016-03-28T17:11:59Z.
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