Ultralow-Voltage Retention SRAM With a Power Gating Cell Architecture Using Header and Footer Power-Switches

Ultralow-Voltage Retention SRAM With a Power Gating Cell Architecture Using Header and Footer Power-Switches

An ultralow-voltage retention SRAM (ULVR-SRAM) cell using header and footer power-switches (HFPSs) is investigated for power-gating (PG) applications. The cell can change its operational mode depending on the cell voltage (<inline-formula> <tex-math notation="LaTeX">${V} _{\mat...

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Bibliographic Details
Main Authors: Hayato Yoshida, Yusaku Shiotsu, Daiki Kitagata, Shuu'ichirou Yamamoto, Satoshi Sugahara
Format: Article
Language:English
Published: IEEE 2021-01-01
Series:IEEE Open Journal of Circuits and Systems
Subjects:
SRAM
cell design
ultralow voltage retention
power gating
standby power
break-even time
Online Access:https://ieeexplore.ieee.org/document/9515125/

Internet

https://ieeexplore.ieee.org/document/9515125/

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