A Low Noise, Low Power Phase-Locked Loop, Using Optimization Methods
A divider-less, low power, and low jitter phase-locked loop (PLL) is presented in this paper. An extra simple open loop phase frequency detector (PFD) is proposed which reduces the power consumption and increases the overall speed. A novel bulk driven Wilson charge pump circuit, whose performance is...
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| Format: | Article |
| Language: | English |
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Hindawi Limited
2016-01-01
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| Series: | Journal of Electrical and Computer Engineering |
| Online Access: | http://dx.doi.org/10.1155/2016/8202581 |
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doaj-f8510a715cce4e33b3e40a57c828d7fd2021-07-02T01:47:05ZengHindawi LimitedJournal of Electrical and Computer Engineering2090-01472090-01552016-01-01201610.1155/2016/82025818202581A Low Noise, Low Power Phase-Locked Loop, Using Optimization MethodsNoushin Ghaderi0Hamid Reza Erfani-jazi1Mehdi Mohseni-Mirabadi2Faculty of Engineering, Shahrekord University, Shahrekord 8818634141, IranFaculty of Engineering, Shahrekord University, Shahrekord 8818634141, IranFaculty of Engineering, Shahrekord University, Shahrekord 8818634141, IranA divider-less, low power, and low jitter phase-locked loop (PLL) is presented in this paper. An extra simple open loop phase frequency detector (PFD) is proposed which reduces the power consumption and increases the overall speed. A novel bulk driven Wilson charge pump circuit, whose performance is enhanced by some optimization algorithms, is also introduced to get high output swing and high current matching. The designed PLL is utilized in a 0.18 μm CMOS process with a 1.8 V power supply. It has a wide locking range frequency of 500 MHz to 5 GHz. In addition, through the use of a dead-zone-less PFD and a divider-less PLL, the overall jitter is decreased significantly.http://dx.doi.org/10.1155/2016/8202581 |
| collection |
DOAJ |
| language |
English |
| format |
Article |
| sources |
DOAJ |
| author |
Noushin Ghaderi Hamid Reza Erfani-jazi Mehdi Mohseni-Mirabadi |
| spellingShingle |
Noushin Ghaderi Hamid Reza Erfani-jazi Mehdi Mohseni-Mirabadi A Low Noise, Low Power Phase-Locked Loop, Using Optimization Methods Journal of Electrical and Computer Engineering |
| author_facet |
Noushin Ghaderi Hamid Reza Erfani-jazi Mehdi Mohseni-Mirabadi |
| author_sort |
Noushin Ghaderi |
| title |
A Low Noise, Low Power Phase-Locked Loop, Using Optimization Methods |
| title_short |
A Low Noise, Low Power Phase-Locked Loop, Using Optimization Methods |
| title_full |
A Low Noise, Low Power Phase-Locked Loop, Using Optimization Methods |
| title_fullStr |
A Low Noise, Low Power Phase-Locked Loop, Using Optimization Methods |
| title_full_unstemmed |
A Low Noise, Low Power Phase-Locked Loop, Using Optimization Methods |
| title_sort |
low noise, low power phase-locked loop, using optimization methods |
| publisher |
Hindawi Limited |
| series |
Journal of Electrical and Computer Engineering |
| issn |
2090-0147 2090-0155 |
| publishDate |
2016-01-01 |
| description |
A divider-less, low power, and low jitter phase-locked loop (PLL) is presented in this paper. An extra simple open loop phase frequency detector (PFD) is proposed which reduces the power consumption and increases the overall speed. A novel bulk driven Wilson charge pump circuit, whose performance is enhanced by some optimization algorithms, is also introduced to get high output swing and high current matching. The designed PLL is utilized in a 0.18 μm CMOS process with a 1.8 V power supply. It has a wide locking range frequency of 500 MHz to 5 GHz. In addition, through the use of a dead-zone-less PFD and a divider-less PLL, the overall jitter is decreased significantly. |
| url |
http://dx.doi.org/10.1155/2016/8202581 |
| work_keys_str_mv |
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1721344457836593152 |