A Low Noise, Low Power Phase-Locked Loop, Using Optimization Methods
A divider-less, low power, and low jitter phase-locked loop (PLL) is presented in this paper. An extra simple open loop phase frequency detector (PFD) is proposed which reduces the power consumption and increases the overall speed. A novel bulk driven Wilson charge pump circuit, whose performance is...
| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
| Published: |
Hindawi Limited
2016-01-01
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| Series: | Journal of Electrical and Computer Engineering |
| Online Access: | http://dx.doi.org/10.1155/2016/8202581 |