Processor Instructions Execution Models in Computer Systems Supporting Hardware Virtualization When an Intruder Takes Detection Countermeasures
We are discussing processor modes switching schemes and analyzing processor instructions execution in the cases when a hypervisor is present in the computer or not. We determine processor instructions execution latency statistics which are applicable for these hypervisors detection when an intruder...
| Main Authors: | , , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
Moscow Engineering Physics Institute
2012-06-01
|
| Series: | Bezopasnostʹ Informacionnyh Tehnologij |
| Subjects: | |
| Online Access: | https://bit.mephi.ru/index.php/bit/article/view/471 |