A V-Band Phase-Locked Loop with a Novel Phase-Frequency Detector in 65 nm CMOS
A 65–67 GHz phase-locked loop (PLL) with a novel low power phase-frequency detector (PFD) in 65 nm LP CMOS is presented. The PLL consists of a V-band voltage-controlled oscillator (VCO), a divide-by-two injection-locked frequency divider (ILFD), and a current-mode logic (CML) divider chain. A charge...
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MDPI AG
2020-09-01
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| Series: | Electronics |
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| Online Access: | https://www.mdpi.com/2079-9292/9/9/1502 |
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doaj-ef2782d266854e379ba63fa3d002b2382020-11-25T03:25:29ZengMDPI AGElectronics2079-92922020-09-0191502150210.3390/electronics9091502A V-Band Phase-Locked Loop with a Novel Phase-Frequency Detector in 65 nm CMOSWaseem Abbas0Zubair Mehmood1Munkyo Seo2Department of Electrical and Computer Engineering, Sungkyunkwan University, Suwon 16419, KoreaDepartment of Electrical and Computer Engineering, Sungkyunkwan University, Suwon 16419, KoreaDepartment of Electrical and Computer Engineering, Sungkyunkwan University, Suwon 16419, KoreaA 65–67 GHz phase-locked loop (PLL) with a novel low power phase-frequency detector (PFD) in 65 nm LP CMOS is presented. The PLL consists of a V-band voltage-controlled oscillator (VCO), a divide-by-two injection-locked frequency divider (ILFD), and a current-mode logic (CML) divider chain. A charge pump (CP) and a 2nd-order loop filter are used with PFD for VCO tuning. The PFD is implemented with 16 transistors with dead-zone-free capability. The measured locking range of the PLL is from 65.15 to 67.4 GHz, with −11.5 dBm measured output power at 66.05 GHz while consuming 88 mW. The measured phase noise at 1 MHz offset is −84.43 dBc/Hz. The chip area of the PLL is 0.84 mm<inline-formula><math display="inline"><semantics><msup><mrow></mrow><mn>2</mn></msup></semantics></math></inline-formula> including probing pads. The proposed PLL can be utilized as a frequency synthesizer for carrier signal generation in IEEE 802.11ad standard high data rate transceiver circuits.https://www.mdpi.com/2079-9292/9/9/1502phase locked loop (PLL)injection locked frequency divider (ILFD)phase and frequency detector (PFD)voltage-controlled oscillator (VCO) |
| collection |
DOAJ |
| language |
English |
| format |
Article |
| sources |
DOAJ |
| author |
Waseem Abbas Zubair Mehmood Munkyo Seo |
| spellingShingle |
Waseem Abbas Zubair Mehmood Munkyo Seo A V-Band Phase-Locked Loop with a Novel Phase-Frequency Detector in 65 nm CMOS Electronics phase locked loop (PLL) injection locked frequency divider (ILFD) phase and frequency detector (PFD) voltage-controlled oscillator (VCO) |
| author_facet |
Waseem Abbas Zubair Mehmood Munkyo Seo |
| author_sort |
Waseem Abbas |
| title |
A V-Band Phase-Locked Loop with a Novel Phase-Frequency Detector in 65 nm CMOS |
| title_short |
A V-Band Phase-Locked Loop with a Novel Phase-Frequency Detector in 65 nm CMOS |
| title_full |
A V-Band Phase-Locked Loop with a Novel Phase-Frequency Detector in 65 nm CMOS |
| title_fullStr |
A V-Band Phase-Locked Loop with a Novel Phase-Frequency Detector in 65 nm CMOS |
| title_full_unstemmed |
A V-Band Phase-Locked Loop with a Novel Phase-Frequency Detector in 65 nm CMOS |
| title_sort |
v-band phase-locked loop with a novel phase-frequency detector in 65 nm cmos |
| publisher |
MDPI AG |
| series |
Electronics |
| issn |
2079-9292 |
| publishDate |
2020-09-01 |
| description |
A 65–67 GHz phase-locked loop (PLL) with a novel low power phase-frequency detector (PFD) in 65 nm LP CMOS is presented. The PLL consists of a V-band voltage-controlled oscillator (VCO), a divide-by-two injection-locked frequency divider (ILFD), and a current-mode logic (CML) divider chain. A charge pump (CP) and a 2nd-order loop filter are used with PFD for VCO tuning. The PFD is implemented with 16 transistors with dead-zone-free capability. The measured locking range of the PLL is from 65.15 to 67.4 GHz, with −11.5 dBm measured output power at 66.05 GHz while consuming 88 mW. The measured phase noise at 1 MHz offset is −84.43 dBc/Hz. The chip area of the PLL is 0.84 mm<inline-formula><math display="inline"><semantics><msup><mrow></mrow><mn>2</mn></msup></semantics></math></inline-formula> including probing pads. The proposed PLL can be utilized as a frequency synthesizer for carrier signal generation in IEEE 802.11ad standard high data rate transceiver circuits. |
| topic |
phase locked loop (PLL) injection locked frequency divider (ILFD) phase and frequency detector (PFD) voltage-controlled oscillator (VCO) |
| url |
https://www.mdpi.com/2079-9292/9/9/1502 |
| work_keys_str_mv |
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