A V-Band Phase-Locked Loop with a Novel Phase-Frequency Detector in 65 nm CMOS
A 65–67 GHz phase-locked loop (PLL) with a novel low power phase-frequency detector (PFD) in 65 nm LP CMOS is presented. The PLL consists of a V-band voltage-controlled oscillator (VCO), a divide-by-two injection-locked frequency divider (ILFD), and a current-mode logic (CML) divider chain. A charge...
Main Authors: | , , |
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Format: | Article |
Language: | English |
Published: |
MDPI AG
2020-09-01
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Series: | Electronics |
Subjects: | |
Online Access: | https://www.mdpi.com/2079-9292/9/9/1502 |