Cross-Corner Delay Variation Model for Standard Cell Libraries

Cross-Corner Delay Variation Model for Standard Cell Libraries

For timing closure of logic circuits, circuit designers must perform sign-offs on a variety of <italic>process, voltage, and temperature (PVT)</italic> conditions. Designs of advanced logic circuits involve a multitude of voltage islands and operating modes, each of which requires delay...

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Bibliographic Details
Main Authors: Kwangsu Kim, Byungha Joo, Young Min Park, Taeyang Jeong, Ki Tae Kim, Eui-Young Chung
Format: Article
Language:English
Published: IEEE 2021-01-01
Series:IEEE Access
Subjects:
CMOS technology
design automation
design tools
integrated circuit synthesis
logic circuits
semiconductor devices
Online Access:https://ieeexplore.ieee.org/document/9431196/

Internet

https://ieeexplore.ieee.org/document/9431196/

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