A Split Island Layout Style of Butting/Inserted Substrate Pickups for NMOSFET ESD Reliability
Butting/inserted pickup layout style could result in severe ESD degradation of NMOS devices beyond deep submicron technology. A split island layout style of butting/inserted substrate pickups is designed for a multifinger NMOS structure to enhance its ESD reliability. This layout style divides the s...
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Online Access: | http://dx.doi.org/10.1155/2015/691403 |
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doaj-eb54608905274dfbbb82501ecc5443e12020-11-24T20:48:56ZengHindawi LimitedAdvances in Materials Science and Engineering1687-84341687-84422015-01-01201510.1155/2015/691403691403A Split Island Layout Style of Butting/Inserted Substrate Pickups for NMOSFET ESD ReliabilityChih-Yao Huang0Fu-Chien Chiu1Bo-Chen Lin2Po-Kung Song3Department of Electronics Engineering, Chien Hsin University of Science and Technology, No. 229, Chien-Hsin Road, Zhongli District, Taoyuan City 320, TaiwanDepartment of Electronic Engineering, Ming Chuan University, No. 5 De Ming Road, Gui-Shan District, Taoyuan City 333, TaiwanProbeLeader Co. Ltd., Hsinchu City 300, TaiwanField Application Engineering Department, Innolux Corp., Miola County 350, TaiwanButting/inserted pickup layout style could result in severe ESD degradation of NMOS devices beyond deep submicron technology. A split island layout style of butting/inserted substrate pickups is designed for a multifinger NMOS structure to enhance its ESD reliability. This layout style divides the substrate pickup diffusion bands along the whole polygate finger direction into segmented diffusion islands in the source area. This layout technique could improve the TLP second breakdown current of the 1.8 V butting pickup structure by 58~66% and 1.8 V/3.3 V inserted pickup case by 2.8 times. This style also shows excellent enhancement for the ESD/HBM levels of the 1.8 V and 3.3 V butting pickup case by 2.1~2.3 times and 18%~6 times, respectively, and the 1.8 V and 3.3 V inserted pickup case by 2.4~2.9 times and 13%~6 times, respectively. This simple technique could restore the ESD threshold level of the butting/inserted pickup layout style back to that of the normal GGNMOS without any further area consumption or fabrication cost.http://dx.doi.org/10.1155/2015/691403 |
collection |
DOAJ |
language |
English |
format |
Article |
sources |
DOAJ |
author |
Chih-Yao Huang Fu-Chien Chiu Bo-Chen Lin Po-Kung Song |
spellingShingle |
Chih-Yao Huang Fu-Chien Chiu Bo-Chen Lin Po-Kung Song A Split Island Layout Style of Butting/Inserted Substrate Pickups for NMOSFET ESD Reliability Advances in Materials Science and Engineering |
author_facet |
Chih-Yao Huang Fu-Chien Chiu Bo-Chen Lin Po-Kung Song |
author_sort |
Chih-Yao Huang |
title |
A Split Island Layout Style of Butting/Inserted Substrate Pickups for NMOSFET ESD Reliability |
title_short |
A Split Island Layout Style of Butting/Inserted Substrate Pickups for NMOSFET ESD Reliability |
title_full |
A Split Island Layout Style of Butting/Inserted Substrate Pickups for NMOSFET ESD Reliability |
title_fullStr |
A Split Island Layout Style of Butting/Inserted Substrate Pickups for NMOSFET ESD Reliability |
title_full_unstemmed |
A Split Island Layout Style of Butting/Inserted Substrate Pickups for NMOSFET ESD Reliability |
title_sort |
split island layout style of butting/inserted substrate pickups for nmosfet esd reliability |
publisher |
Hindawi Limited |
series |
Advances in Materials Science and Engineering |
issn |
1687-8434 1687-8442 |
publishDate |
2015-01-01 |
description |
Butting/inserted pickup layout style could result in severe ESD degradation of NMOS devices beyond deep submicron technology. A split island layout style of butting/inserted substrate pickups is designed for a multifinger NMOS structure to enhance its ESD reliability. This layout style divides the substrate pickup diffusion bands along the whole polygate finger direction into segmented diffusion islands in the source area. This layout technique could improve the TLP second breakdown current of the 1.8 V butting pickup structure by 58~66% and 1.8 V/3.3 V inserted pickup case by 2.8 times. This style also shows excellent enhancement for the ESD/HBM levels of the 1.8 V and 3.3 V butting pickup case by 2.1~2.3 times and 18%~6 times, respectively, and the 1.8 V and 3.3 V inserted pickup case by 2.4~2.9 times and 13%~6 times, respectively. This simple technique could restore the ESD threshold level of the butting/inserted pickup layout style back to that of the normal GGNMOS without any further area consumption or fabrication cost. |
url |
http://dx.doi.org/10.1155/2015/691403 |
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