Hardware Optimized and Error Reduced Approximate Adder

Hardware Optimized and Error Reduced Approximate Adder

This paper presents a new hardware optimized and error reduced approximate adder (HOERAA), which is suitable for field programmable gate array (FPGA)- and application specific integrated circuit (ASIC)-based implementations. In this work, we consider a FPGA-based implementation using Xilinx Vivado 2...

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Bibliographic Details
Main Authors: Padmanabhan Balasubramanian, Douglas L. Maskell
Format: Article
Language:English
Published: MDPI AG 2019-10-01
Series:Electronics
Subjects:
approximate computing
approximate adder
arithmetic circuits
field programmable gate array (fpga)
application specific integrated circuit (asic)
low power
high speed
Online Access:https://www.mdpi.com/2079-9292/8/11/1212

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