Hardware-Efficient Delta Sigma-Based Digital Signal Processing Circuits for the Internet-of-Things

Hardware-Efficient Delta Sigma-Based Digital Signal Processing Circuits for the Internet-of-Things

This paper presents hardware-efficient Delta Sigma linear processing circuits for the next generation low-power VLSI devices in the Internet-of-things (IoT).We first propose the P-N (positive-negative) pair method to manipulate both the analog value and length of a first-order Delta Sigma bit sequen...

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Bibliographic Details
Main Authors: Yifei Liu, Paul M. Furth, Wei Tang
Format: Article
Language:English
Published: MDPI AG 2015-11-01
Series:Journal of Low Power Electronics and Applications
Subjects:
VLSI
Delta Sigma modulation
digital signal processing
adder
coefficient multiplier
low-power low-complexity circuits
Online Access:http://www.mdpi.com/2079-9268/5/4/234

Internet

http://www.mdpi.com/2079-9268/5/4/234

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