Design of a Highly Robust Triple-Node-Upset Self-Recoverable Latch

Design of a Highly Robust Triple-Node-Upset Self-Recoverable Latch

Due to semiconductor technology scaling, integrated circuits have become more sensitive to soft errors. To effectively tolerate multi-node-upsets caused by soft errors and reduce the power dissipation and delay of a latch, this paper proposes a novel triple-node-upset (TNU) self-recoverable latch de...

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Bibliographic Details
Main Authors: Hui Xu, Cong Sun, Le Zhou, Huaguo Liang, Zhengfeng Huang
Format: Article
Language:English
Published: IEEE 2021-01-01
Series:IEEE Access
Subjects:
Soft errors
self-recoverable
triple-node-upset
clock gating
high-speed transmission path
Online Access:https://ieeexplore.ieee.org/document/9512035/

Internet

https://ieeexplore.ieee.org/document/9512035/

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