Area Efficient Dual-Fed CMOS Distributed Power Amplifier

Area Efficient Dual-Fed CMOS Distributed Power Amplifier

In this paper, an area-efficient 4-stage dual-fed distributed power amplifier (DPA) implemented in a 0.35 μm Complementary Metal Oxide Semiconductor (CMOS) process is presented. To effectively reduce the area of the circuit, techniques such as using multilevel inductors and closely-placing co...

Full description

Bibliographic Details
Main Authors: Javier del Pino, Sunil L. Khemchandani, Sergio Mateos-Angulo, Daniel Mayor-Duarte, Mario San-Miguel-Montesdeoca
Format: Article
Language:English
Published: MDPI AG 2018-08-01
Series:Electronics
Subjects:
distributed power amplifier
dual-fed
stacked inductor
multilevel inductor
area reduction
Online Access:http://www.mdpi.com/2079-9292/7/8/139

Internet

http://www.mdpi.com/2079-9292/7/8/139

Similar Items