A Low-Power High-Speed Dynamic Comparator With a Transconductance-Enhanced Latching Stage

A Low-Power High-Speed Dynamic Comparator With a Transconductance-Enhanced Latching Stage

Low-power, high-speed dynamic comparators are highly desirable in the design of high-speed analog-to-digital converters (ADC) and digital I/O circuits. Most dynamic comparators use a pair of cross-coupled inverters as the latching stage, which provides strong positive feedback, to accelerate the com...

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Bibliographic Details
Main Authors: Yao Wang, Mengmeng Yao, Benqing Guo, Zhaolei Wu, Wenbing Fan, Juin Jei Liou
Format: Article
Language:English
Published: IEEE 2019-01-01
Series:IEEE Access
Subjects:
Dynamic comparator
high-speed
low-power
two-stage comparator
Online Access:https://ieeexplore.ieee.org/document/8758098/

Internet

https://ieeexplore.ieee.org/document/8758098/

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