Si-ring quantum-well GAA nanowire FET for 5 nm node CMOS integration
A novel structure for gate all-around (GAA) NW FET in the 5 nm scale has been proposed in this paper. This device consists of a germanium nanowire structure, the channel of which is surrounded by a ring-shaped silicon layer. In addition, a high-K dielectric has been used as the gate insulator. The p...
Main Authors: | Payman Bahrami, Mohammad Reza Shayesteh, Majid Pourahmadi, Hadi Safdarkhani |
---|---|
Format: | Article |
Language: | English |
Published: |
AIP Publishing LLC
2020-08-01
|
Series: | AIP Advances |
Online Access: | http://dx.doi.org/10.1063/5.0013544 |
Similar Items
-
Series Resistance Reduction in Stacked Nanowire FETs for 7-nm CMOS Technology
by: Anil Kumar Bansal, et al.
Published: (2016-01-01) -
The Evaluation of 6T-SRAM for GAA MOSFETs and FinFETs at 7 nm and 10 nm Technology Nodes
by: Meng-YenWu, et al.
Published: (2016) -
GAAFET Versus Pragmatic FinFET at the 5nm Si-Based CMOS Technology Node
by: Ya-Chi Huang, et al.
Published: (2017-01-01) -
Study of Junctionless GAA nanowire FETs with extended gate as Biosensors
by: Chiang, Li-Chuan, et al.
Published: (2015) -
Benchmarking of FinFET, Nanosheet, and Nanowire FET Architectures for Future Technology Nodes
by: Daniel Nagy, et al.
Published: (2020-01-01)