Sensitivity Improvement of a Fully Symmetric Vertical Hall Device Fabricated in 0.18 μm Low-Voltage CMOS Technology

• Main Authors: Haiyun Huang, Yue Xu
• Format: Article
• Language: English
• Published: IEEE 2021-01-01
• Series: IEEE Journal of the Electron Devices Society
• Subjects: Vertical hall device; magnetic sensitivity; trench; standard CMOS 14 technology
• Online Access: https://ieeexplore.ieee.org/document/9534868/

This paper proposes a new implementation method to significantly improve the magnetic sensitivity of a fully symmetric vertical Hall device (FSVHD) based on low-voltage CMOS technology. The FSVHD consists of four identical three-contact vertical Hall elements (3CVHE) and each 3CVHE is located in a low-doped deep n-well. The terminals of the 3CVHE are <inline-formula> <tex-math notation="LaTeX">$\text{n}^{+}$ </tex-math></inline-formula> implanted in an n-well and a <inline-formula> <tex-math notation="LaTeX">$\text{p}^{+}$ </tex-math></inline-formula> implantation in a p-well is performed to act as a trench between two adjacent <inline-formula> <tex-math notation="LaTeX">$\text{n}^{+}$ </tex-math></inline-formula> contacts, enabling Hall current flowing deeply for sensitivity improvement. The influence of the geometry sizes on magnetic sensitivity is exploited utilizing TCAD simulation to obtain the optimized device structure in a <inline-formula> <tex-math notation="LaTeX">$0.18~\mu\text{m}$ </tex-math></inline-formula> CMOS standard technology. The experimental results reveal that the proposed FSVHD with a <inline-formula> <tex-math notation="LaTeX">$\text{p}^{+}$ </tex-math></inline-formula>/p-well trench can attain an improved voltage-related sensitivity of 8.4 mV/VT, which is about 70&#x0025; higher than that of a conventional FSVHD without a trench in the same CMOS fabrication process, while offset and noise are not degraded. The proposed <inline-formula> <tex-math notation="LaTeX">$\text{p}^{+}$ </tex-math></inline-formula>/p-well implantation trench is a good solution to enhance the sensitivity of a low-voltage CMOS VHD with a low manufacturing cost.