Analyzing the Effects of Interconnect Parasitics in the STT CRAM In-Memory Computational Platform

• Main Authors: Masoud Zabihi, Arvind K. Sharma, Meghna G. Mankalale, Zamshed Iqbal Chowdhury, Zhengyang Zhao, Salonik Resch, Ulya R. Karpuzcu, Jian-Ping Wang, Sachin S. Sapatnekar
• Format: Article
• Language: English
• Published: IEEE 2020-01-01
• Series: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
• Subjects: In-memory computing; spin-transfer torque computational random access memory (STT-CRAM); spintronics
• Online Access: https://ieeexplore.ieee.org/document/9056847/
• ISSN: 2329-9231

This article presents a method for analyzing the parasitic effects of interconnects on the performance of the STT-MTJ-based computational random access memory (CRAM) in-memory computation platform. The CRAM is a platform that makes a small reconfiguration to a standard spintronics-based memory array to enable logic operations within the array. The analytical method in this article develops a methodology that quantifies the way in which wire parasitics limit the size and configuration of a CRAM array and studies the impact of cell- and array-level design choices on the CRAM noise margin. Finally, the method determines the maximum allowable CRAM array size under various technology considerations.