Genetic Algorithm-based thermal uniformity–aware X-filling to reduce peak temperature during testing
High temperature occurs in testing of complex System-on-Chip designs and it may become a critical concern to be carefully taken into account with continual development in Very Large Scale Integration technology. Peak temperature significantly affects the reliability and the performance of the chip....
| Main Authors: | , |
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| Format: | Article |
| Language: | English |
| Published: |
SAGE Publishing
2018-09-01
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| Series: | Measurement + Control |
| Online Access: | https://doi.org/10.1177/0020294018784969 |
| Summary: | High temperature occurs in testing of complex System-on-Chip designs and it may become a critical concern to be carefully taken into account with continual development in Very Large Scale Integration technology. Peak temperature significantly affects the reliability and the performance of the chip. So it is essential to minimize the peak temperature of the chip. Heat generation by power consumption and heat dissipation to the surrounding blocks are the two prominent factors for the peak temperature. Power consumption can be minimized by a careful mapping of don’t cares in precomputed test set. However, it does not provide the solution to peak temperature minimization because the non-uniformity in spatial power distribution may create localized heating event called “hotspot.” The peak temperature on the hotspot is minimized by Genetic Algorithm–based don’t care filling technique that reduces the non-uniformity in spatial power distribution within the circuit under test while maintaining the overall power consumption at a lower level. Experimental results on ISCAS89 benchmark circuits demonstrate that 6%–28% peak temperature reduction can be achieved. |
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| ISSN: | 0020-2940 |