Parasitic Loop Inductances Reduction in the PCB Layout in GaN-Based Power Converters Using S-Parameters and EM Simulations

Parasitic Loop Inductances Reduction in the PCB Layout in GaN-Based Power Converters Using S-Parameters and EM Simulations

Due to the high switching speed of Gallium Nitride (GaN) transistors, parasitic inductances have significant impacts on power losses and electromagnetic interferences (EMI) in GaN-based power converters. Thus, the proper design of high-frequency converters in a simulation tool requires accurate elec...

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Bibliographic Details
Main Authors: Loris Pace, Nadir Idir, Thierry Duquesne, Jean-Claude De Jaeger
Format: Article
Language:English
Published: MDPI AG 2021-03-01
Series:Energies
Subjects:
GaN converter
commutation loop inductance
PCB layout
S-parameter
EM modeling
EMI
Online Access:https://www.mdpi.com/1996-1073/14/5/1495

Internet

https://www.mdpi.com/1996-1073/14/5/1495

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