Methodology for validating Nest Memory Management Unit

• Main Authors: Nandhini Rajaiah, Jayakumar Sankarannair, Larry Leitner
• Format: Article
• Language: English
• Published: European Alliance for Innovation (EAI) 2019-03-01
• Series: EAI Endorsed Transactions on Cloud Systems
• Subjects: post-silicon validation; address translation mechanisms; microprocessor; accelerator; design verification
• Online Access: https://eudl.eu/pdf/10.4108/eai.15-3-2019.162139

The growing demand for performance makes the processor logic design more complex, thereby making post-silicon validation a critical and complex step in processor development life cycle. There are complex units with newer timing and control logic paths which are almost impossible to exercise in regular verification environments. One such unit to cater to newer workloads in recent superscalar processors is the Nest Memory Management Unit (NMMU), a memorymanagement unit for all I/O devices. This paper presents some of the major challenges in validating Nest MMU. A postsilicon validation framework is proposed to mitigate these challenges. An asynchronous non-blocking accelerator jobsubmission model is used in this approach to increase the translation traffic from the agent to NMMU. Core MMU translation is used as the reference model to validate nest MMU. The processor core storage exception handlers are leveraged to minimize the validation tool software development effort and to increase the efficiency of validation as well.This method makes use of an optimized threshold-based checker to detect potential NMMU hardware issues. The proposed methodology has been experimentally evaluated in Power9 NMMU to demonstrate the effectiveness of the method in providing considerable stress to the unit.