Methodology for validating Nest Memory Management Unit
The growing demand for performance makes the processor logic design more complex, thereby making post-silicon validation a critical and complex step in processor development life cycle. There are complex units with newer timing and control logic paths which are almost impossible to exercise in regul...
| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
| Published: |
European Alliance for Innovation (EAI)
2019-03-01
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| Series: | EAI Endorsed Transactions on Cloud Systems |
| Subjects: | |
| Online Access: | https://eudl.eu/pdf/10.4108/eai.15-3-2019.162139 |