Design and Implementation of a 256-Bit RISC-V-Based Dynamically Scheduled Very Long Instruction Word on FPGA

Design and Implementation of a 256-Bit RISC-V-Based Dynamically Scheduled Very Long Instruction Word on FPGA

This study describes the design and implementation of a 256-bit very long instruction word (VLIW) microprocessor based on the new RISC-V instruction set architecture (ISA). Base integer RV32I and extension instruction sets, including RV32M, RV32F, and RV32D, are selected to implement our VLIW hardwa...

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Bibliographic Details
Main Authors: Nguyen My Qui, Chang Hong Lin, Poki Chen
Format: Article
Language:English
Published: IEEE 2020-01-01
Series:IEEE Access
Subjects:
Very long instruction word (VLIW)
RISC-V
microprocessor
dynamic scheduling
field-programmable gate arrays (FPGA)
Online Access:https://ieeexplore.ieee.org/document/9200617/

Internet

https://ieeexplore.ieee.org/document/9200617/

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