Fully CMOS Memristor Based Chaotic Circuit
This paper demonstrates the design of a fully CMOS chaotic circuit consisting of only DDCC based memristor and inductance simulator. Our design is composed of these active blocks using CMOS 0.18 µm process technology with symmetric ±1.25 V supply voltages. A new single DDCC+ based topology is used a...
| Main Authors: | , |
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| Format: | Article |
| Language: | English |
| Published: |
Spolecnost pro radioelektronicke inzenyrstvi
2014-12-01
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| Series: | Radioengineering |
| Subjects: | |
| Online Access: | http://www.radioeng.cz/fulltexts/2014/14_04_1140_1149.pdf |