Power Gating Technique for Power Reduction and Data Retention in CMOS Circuits

Power Gating Technique for Power Reduction and Data Retention in CMOS Circuits

Usage of battery powered hand held devices has been increasing in this modern era. To extend the battery life of these devices, more aggressive power reduction techniques are necessary. Power gating techniques are commonly used for suppressing leakage in digital VLSI circuits. In this paper a pow...

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Bibliographic Details
Main Authors: MANICKAM Kavitha, THANGAVEL Govindaraj
Format: Article
Language:English
Published: Editura Universităţii din Oradea 2016-05-01
Series:Journal of Electrical and Electronics Engineering
Subjects:
leakage power
power gating
data retention
drowsy mode
charge recycling
stack effect
Online Access:http://electroinf.uoradea.ro/images/articles/CERCETARE/Reviste/JEEE/JEEE_V9_N1_MAY_2016/Manickam_JEEE_Vol_9_Nr_1_MAY_2016.pdf
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spelling doaj-d28ac11c24884dad8ce2439b00f50b872020-11-24T21:32:08ZengEditura Universităţii din OradeaJournal of Electrical and Electronics Engineering1844-60352067-21282016-05-01911924Power Gating Technique for Power Reduction and Data Retention in CMOS CircuitsMANICKAM Kavitha0THANGAVEL Govindaraj1Anna University, India, Department of ECE, Faculty of Information and Communication EngineeringAnna University, India, Department of EEE, Faculty of Information and Communication EngineeringUsage of battery powered hand held devices has been increasing in this modern era. To extend the battery life of these devices, more aggressive power reduction techniques are necessary. Power gating techniques are commonly used for suppressing leakage in digital VLSI circuits. In this paper a power gating technique is proposed for efficient leakage reduction and data retention. The simulation results reveal that the proposed technique exhibits 84-93% leakage reduction, 7-28% drowsy power reduction, 4-30% dynamic power reduction compared to conventional technique. Proposed technique also provides good data stability than existing technique.http://electroinf.uoradea.ro/images/articles/CERCETARE/Reviste/JEEE/JEEE_V9_N1_MAY_2016/Manickam_JEEE_Vol_9_Nr_1_MAY_2016.pdfleakage powerpower gatingdata retentiondrowsy modecharge recyclingstack effect
collection DOAJ
language English
format Article
sources DOAJ
author MANICKAM Kavitha
THANGAVEL Govindaraj
spellingShingle MANICKAM Kavitha
THANGAVEL Govindaraj
Power Gating Technique for Power Reduction and Data Retention in CMOS Circuits
Journal of Electrical and Electronics Engineering
leakage power
power gating
data retention
drowsy mode
charge recycling
stack effect
author_facet MANICKAM Kavitha
THANGAVEL Govindaraj
author_sort MANICKAM Kavitha
title Power Gating Technique for Power Reduction and Data Retention in CMOS Circuits
title_short Power Gating Technique for Power Reduction and Data Retention in CMOS Circuits
title_full Power Gating Technique for Power Reduction and Data Retention in CMOS Circuits
title_fullStr Power Gating Technique for Power Reduction and Data Retention in CMOS Circuits
title_full_unstemmed Power Gating Technique for Power Reduction and Data Retention in CMOS Circuits
title_sort power gating technique for power reduction and data retention in cmos circuits
publisher Editura Universităţii din Oradea
series Journal of Electrical and Electronics Engineering
issn 1844-6035
2067-2128
publishDate 2016-05-01
description Usage of battery powered hand held devices has been increasing in this modern era. To extend the battery life of these devices, more aggressive power reduction techniques are necessary. Power gating techniques are commonly used for suppressing leakage in digital VLSI circuits. In this paper a power gating technique is proposed for efficient leakage reduction and data retention. The simulation results reveal that the proposed technique exhibits 84-93% leakage reduction, 7-28% drowsy power reduction, 4-30% dynamic power reduction compared to conventional technique. Proposed technique also provides good data stability than existing technique.
topic leakage power
power gating
data retention
drowsy mode
charge recycling
stack effect
url http://electroinf.uoradea.ro/images/articles/CERCETARE/Reviste/JEEE/JEEE_V9_N1_MAY_2016/Manickam_JEEE_Vol_9_Nr_1_MAY_2016.pdf
work_keys_str_mv AT manickamkavitha powergatingtechniqueforpowerreductionanddataretentionincmoscircuits
AT thangavelgovindaraj powergatingtechniqueforpowerreductionanddataretentionincmoscircuits
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