Power Gating Technique for Power Reduction and Data Retention in CMOS Circuits

Power Gating Technique for Power Reduction and Data Retention in CMOS Circuits

Usage of battery powered hand held devices has been increasing in this modern era. To extend the battery life of these devices, more aggressive power reduction techniques are necessary. Power gating techniques are commonly used for suppressing leakage in digital VLSI circuits. In this paper a pow...

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Bibliographic Details
Main Authors: MANICKAM Kavitha, THANGAVEL Govindaraj
Format: Article
Language:English
Published: Editura Universităţii din Oradea 2016-05-01
Series:Journal of Electrical and Electronics Engineering
Subjects:
leakage power
power gating
data retention
drowsy mode
charge recycling
stack effect
Online Access:http://electroinf.uoradea.ro/images/articles/CERCETARE/Reviste/JEEE/JEEE_V9_N1_MAY_2016/Manickam_JEEE_Vol_9_Nr_1_MAY_2016.pdf
Description
Summary:Usage of battery powered hand held devices has been increasing in this modern era. To extend the battery life of these devices, more aggressive power reduction techniques are necessary. Power gating techniques are commonly used for suppressing leakage in digital VLSI circuits. In this paper a power gating technique is proposed for efficient leakage reduction and data retention. The simulation results reveal that the proposed technique exhibits 84-93% leakage reduction, 7-28% drowsy power reduction, 4-30% dynamic power reduction compared to conventional technique. Proposed technique also provides good data stability than existing technique.
ISSN:1844-6035
2067-2128

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