Design of the distributed Cache for reconfigurable array processor
With the increasing number of processor cores integrated on-chip, the problem of “storage walls” in reconfigurable array processors is increasing. Traditionally, the use of multi-level shared Cache hardware design has high complexity and limited parallel access, and it is difficult to meet the memor...
| Main Authors: | , , , , |
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| Format: | Article |
| Language: | zho |
| Published: |
National Computer System Engineering Research Institute of China
2018-12-01
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| Series: | Dianzi Jishu Yingyong |
| Subjects: | |
| Online Access: | http://www.chinaaet.com/article/3000094709 |