VIPVS accelerating 7 nm analog layout design
As GLOBALFOUNDRIES continues design in 7 nm technology for high speed Serdes IP, it should be noted that the complexity of layout design has increased. New challenges include complex DRC verification and complex MPT methodology in the design flow. It is therefore important to develop a layout flow(a...
| Main Authors: | , , , , , , , |
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| Format: | Article |
| Language: | zho |
| Published: |
National Computer System Engineering Research Institute of China
2018-08-01
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| Series: | Dianzi Jishu Yingyong |
| Subjects: | |
| Online Access: | http://www.chinaaet.com/article/3000087794 |