Implementation of the Least-Squares Lattice with Order and Forgetting Factor Estimation for FPGA
A high performance RLS lattice filter with the estimation of an unknown order and forgetting factor of identified system was developed and implemented as a PCORE coprocessor for Xilinx EDK. The coprocessor implemented in FPGA hardware can fully exploit parallelisms in the algorithm and remove load f...
| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
| Published: |
SpringerOpen
2008-08-01
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| Series: | EURASIP Journal on Advances in Signal Processing |
| Online Access: | http://dx.doi.org/10.1155/2008/394201 |