Vedic Mathematics Based 32-Bit Multiplier Design for High Speed Low Power Processors
| Main Authors: | , , , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
Exeley Inc.
2011-06-01
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| Series: | International Journal on Smart Sensing and Intelligent Systems |
| Subjects: | |
| Online Access: | https://www.exeley.com/exeley/journals/in_jour_smart_sensing_and_intelligent_systems/4/2/pdf/10.21307_ijssis-2017-439.pdf |