Novel 10-nm Gate Length MoS<sub>2</sub> Transistor Fabricated on Si Fin Substrate

Novel 10-nm Gate Length MoS<sub>2</sub> Transistor Fabricated on Si Fin Substrate

To allow the use of molybdenum disulfide (MoS<sub>2</sub>) in mainstream Si CMOS manufacturing processes for improved future scaling, a novel MoS<sub>2</sub> transistor with a 10-nm physical gate length created using a p-type doped Si fin as the back-gate electrode is present...

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Bibliographic Details
Main Authors: Yu Pan, Huaxiang Yin, Kailiang Huang, Zhaohao Zhang, Qingzhu Zhang, Kunpeng Jia, Zhenhua Wu, Kun Luo, Jiahan Yu, Junfeng Li, Wenwu Wang, Tianchun Ye
Format: Article
Language:English
Published: IEEE 2019-01-01
Series:IEEE Journal of the Electron Devices Society
Subjects:
MoS₂ transistor
FinFET
Si fin
short gate length
Online Access:https://ieeexplore.ieee.org/document/8686079/

Internet

https://ieeexplore.ieee.org/document/8686079/

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