Novel 10-nm Gate Length MoS<sub>2</sub> Transistor Fabricated on Si Fin Substrate
To allow the use of molybdenum disulfide (MoS<sub>2</sub>) in mainstream Si CMOS manufacturing processes for improved future scaling, a novel MoS<sub>2</sub> transistor with a 10-nm physical gate length created using a p-type doped Si fin as the back-gate electrode is present...
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2019-01-01
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| Series: | IEEE Journal of the Electron Devices Society |
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| Online Access: | https://ieeexplore.ieee.org/document/8686079/ |
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doaj-af22f27b75b44b9483f96c4f5f8995502021-04-05T16:57:09ZengIEEEIEEE Journal of the Electron Devices Society2168-67342019-01-01748348810.1109/JEDS.2019.29102718686079Novel 10-nm Gate Length MoS<sub>2</sub> Transistor Fabricated on Si Fin SubstrateYu Pan0Huaxiang Yin1https://orcid.org/0000-0001-8066-6002Kailiang Huang2Zhaohao Zhang3https://orcid.org/0000-0002-1583-9939Qingzhu Zhang4https://orcid.org/0000-0003-0035-0652Kunpeng Jia5Zhenhua Wu6https://orcid.org/0000-0003-4552-883XKun Luo7Jiahan Yu8https://orcid.org/0000-0001-5187-6588Junfeng Li9Wenwu Wang10Tianchun Ye11https://orcid.org/0000-0002-2384-9037Key Laboratory of Microelectronics Devices and Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing, ChinaKey Laboratory of Microelectronics Devices and Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing, ChinaUniversity of Chinese Academy of Sciences, Beijing, ChinaKey Laboratory of Microelectronics Devices and Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing, ChinaKey Laboratory of Microelectronics Devices and Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing, ChinaKey Laboratory of Microelectronics Devices and Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing, ChinaKey Laboratory of Microelectronics Devices and Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing, ChinaKey Laboratory of Microelectronics Devices and Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing, ChinaKey Laboratory of Microelectronics Devices and Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing, ChinaKey Laboratory of Microelectronics Devices and Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing, ChinaKey Laboratory of Microelectronics Devices and Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing, ChinaKey Laboratory of Microelectronics Devices and Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing, ChinaTo allow the use of molybdenum disulfide (MoS<sub>2</sub>) in mainstream Si CMOS manufacturing processes for improved future scaling, a novel MoS<sub>2</sub> transistor with a 10-nm physical gate length created using a p-type doped Si fin as the back-gate electrode is presented. The fabrication technology of the ultra-small MoS<sub>2</sub> device shows fully process compatibility with conventional Si-FinFET process flow and it is also the first time to realize the large-scale fabrication of the arrayed MoS<sub>2</sub> transistors with 10-nm gate lengths. The fabricated ultrathin transistors, consisting of 10-nm gate length and 0.7-nm monolayer CVD MoS2, exhibit good switching characteristics and the average drain current on/off ratio reaches to over 10<sup>6</sup>. This technology provides a promising approach for future CMOS scaling with large scale new 2-D material transistors.https://ieeexplore.ieee.org/document/8686079/MoS₂ transistorFinFETSi finshort gate length |
| collection |
DOAJ |
| language |
English |
| format |
Article |
| sources |
DOAJ |
| author |
Yu Pan Huaxiang Yin Kailiang Huang Zhaohao Zhang Qingzhu Zhang Kunpeng Jia Zhenhua Wu Kun Luo Jiahan Yu Junfeng Li Wenwu Wang Tianchun Ye |
| spellingShingle |
Yu Pan Huaxiang Yin Kailiang Huang Zhaohao Zhang Qingzhu Zhang Kunpeng Jia Zhenhua Wu Kun Luo Jiahan Yu Junfeng Li Wenwu Wang Tianchun Ye Novel 10-nm Gate Length MoS<sub>2</sub> Transistor Fabricated on Si Fin Substrate IEEE Journal of the Electron Devices Society MoS₂ transistor FinFET Si fin short gate length |
| author_facet |
Yu Pan Huaxiang Yin Kailiang Huang Zhaohao Zhang Qingzhu Zhang Kunpeng Jia Zhenhua Wu Kun Luo Jiahan Yu Junfeng Li Wenwu Wang Tianchun Ye |
| author_sort |
Yu Pan |
| title |
Novel 10-nm Gate Length MoS<sub>2</sub> Transistor Fabricated on Si Fin Substrate |
| title_short |
Novel 10-nm Gate Length MoS<sub>2</sub> Transistor Fabricated on Si Fin Substrate |
| title_full |
Novel 10-nm Gate Length MoS<sub>2</sub> Transistor Fabricated on Si Fin Substrate |
| title_fullStr |
Novel 10-nm Gate Length MoS<sub>2</sub> Transistor Fabricated on Si Fin Substrate |
| title_full_unstemmed |
Novel 10-nm Gate Length MoS<sub>2</sub> Transistor Fabricated on Si Fin Substrate |
| title_sort |
novel 10-nm gate length mos<sub>2</sub> transistor fabricated on si fin substrate |
| publisher |
IEEE |
| series |
IEEE Journal of the Electron Devices Society |
| issn |
2168-6734 |
| publishDate |
2019-01-01 |
| description |
To allow the use of molybdenum disulfide (MoS<sub>2</sub>) in mainstream Si CMOS manufacturing processes for improved future scaling, a novel MoS<sub>2</sub> transistor with a 10-nm physical gate length created using a p-type doped Si fin as the back-gate electrode is presented. The fabrication technology of the ultra-small MoS<sub>2</sub> device shows fully process compatibility with conventional Si-FinFET process flow and it is also the first time to realize the large-scale fabrication of the arrayed MoS<sub>2</sub> transistors with 10-nm gate lengths. The fabricated ultrathin transistors, consisting of 10-nm gate length and 0.7-nm monolayer CVD MoS2, exhibit good switching characteristics and the average drain current on/off ratio reaches to over 10<sup>6</sup>. This technology provides a promising approach for future CMOS scaling with large scale new 2-D material transistors. |
| topic |
MoS₂ transistor FinFET Si fin short gate length |
| url |
https://ieeexplore.ieee.org/document/8686079/ |
| work_keys_str_mv |
AT yupan novel10nmgatelengthmossub2subtransistorfabricatedonsifinsubstrate AT huaxiangyin novel10nmgatelengthmossub2subtransistorfabricatedonsifinsubstrate AT kailianghuang novel10nmgatelengthmossub2subtransistorfabricatedonsifinsubstrate AT zhaohaozhang novel10nmgatelengthmossub2subtransistorfabricatedonsifinsubstrate AT qingzhuzhang novel10nmgatelengthmossub2subtransistorfabricatedonsifinsubstrate AT kunpengjia novel10nmgatelengthmossub2subtransistorfabricatedonsifinsubstrate AT zhenhuawu novel10nmgatelengthmossub2subtransistorfabricatedonsifinsubstrate AT kunluo novel10nmgatelengthmossub2subtransistorfabricatedonsifinsubstrate AT jiahanyu novel10nmgatelengthmossub2subtransistorfabricatedonsifinsubstrate AT junfengli novel10nmgatelengthmossub2subtransistorfabricatedonsifinsubstrate AT wenwuwang novel10nmgatelengthmossub2subtransistorfabricatedonsifinsubstrate AT tianchunye novel10nmgatelengthmossub2subtransistorfabricatedonsifinsubstrate |
| _version_ |
1721540635219984384 |