Novel 10-nm Gate Length MoS₂ Transistor Fabricated on Si Fin Substrate

• Main Authors: Yu Pan, Huaxiang Yin, Kailiang Huang, Zhaohao Zhang, Qingzhu Zhang, Kunpeng Jia, Zhenhua Wu, Kun Luo, Jiahan Yu, Junfeng Li, Wenwu Wang, Tianchun Ye
• Format: Article
• Language: English
• Published: IEEE 2019-01-01
• Series: IEEE Journal of the Electron Devices Society
• Subjects: MoS₂ transistor; FinFET; Si fin; short gate length
• Online Access: https://ieeexplore.ieee.org/document/8686079/
• ISSN: 2168-6734

To allow the use of molybdenum disulfide (MoS₂) in mainstream Si CMOS manufacturing processes for improved future scaling, a novel MoS₂ transistor with a 10-nm physical gate length created using a p-type doped Si fin as the back-gate electrode is presented. The fabrication technology of the ultra-small MoS₂ device shows fully process compatibility with conventional Si-FinFET process flow and it is also the first time to realize the large-scale fabrication of the arrayed MoS₂ transistors with 10-nm gate lengths. The fabricated ultrathin transistors, consisting of 10-nm gate length and 0.7-nm monolayer CVD MoS2, exhibit good switching characteristics and the average drain current on/off ratio reaches to over 10⁶. This technology provides a promising approach for future CMOS scaling with large scale new 2-D material transistors.