A Novel Low-Power Synchronous Preamble Data Line Chip Design for Oscillator Control Interface

A Novel Low-Power Synchronous Preamble Data Line Chip Design for Oscillator Control Interface

In this paper, a novel low-power synchronous preamble data line protocol chip design for serial communication is proposed. The serial communication only uses two wires, chip select (CS) and secure digital (SD), to transmit and receive data between two devices. The proposed protocol aims to use a few...

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Bibliographic Details
Main Authors: Shih-Lun Chen, Tsun-Kuang Chi, Min-Chun Tuan, Chiung-An Chen, Liang-Hung Wang, Wei-Yuan Chiang, Ming-Yi Lin, Patricia Angela R. Abu
Format: Article
Language:English
Published: MDPI AG 2020-09-01
Series:Electronics
Subjects:
SPI
digital signal process
communication protocols
CMOS digital integrated circuit
field-programmable gate array (FPGA)
electronic device measurement and very-large-scale integration (VLSI)
Online Access:https://www.mdpi.com/2079-9292/9/9/1509

Internet

https://www.mdpi.com/2079-9292/9/9/1509

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