Extended Lock Range Zero-Crossing Digital Phase-Locked Loop with Time Delay
<p>The input frequency limit of the conventional zero-crossing digital phase-locked loop (ZCDPLL) is due to the operating time of the digital circuitry inside the feedback loop. A solution that has been previously suggested is the introduction of a time delay in the feedback path of the loop t...
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| Format: | Article |
| Language: | English |
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SpringerOpen
2005-01-01
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| Series: | EURASIP Journal on Wireless Communications and Networking |
| Subjects: | |
| Online Access: | http://dx.doi.org/10.1155/WCN.2005.413 |
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