Low-Cost Soft Error Robust Hardened D-Latch for CMOS Technology Circuit

Low-Cost Soft Error Robust Hardened D-Latch for CMOS Technology Circuit

In this paper, a Soft Error Hardened D-latch with improved performance is proposed, also featuring Single Event Upset (SEU) and Single Event Transient (SET) immunity. This novel D-latch can tolerate particles as charge injection in different internal nodes, as well as the input and output nodes. The...

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Bibliographic Details
Main Authors: Seyedehsomayeh Hatefinasab, Noel Rodriguez, Antonio García, Encarnacion Castillo
Format: Article
Language:English
Published: MDPI AG 2021-05-01
Series:Electronics
Subjects:
Hardened D-latch
Complementary Metal Oxide Semiconductor (CMOS) technology
Power-Delay Product (PDP)
Soft Error (SE)
SEU (Single Event Upset)
High Impedance State (HIS)
Online Access:https://www.mdpi.com/2079-9292/10/11/1256

Internet

https://www.mdpi.com/2079-9292/10/11/1256

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